Hardware Emulation Lab Engineering Lead

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience managing enterprise emulation hardware environments (e.g., Palladium, Protium, or ZeBu).
• Experience managing infrastructure deployments, including physical lab operations, rack installations, power/cooling distribution, and site compliance.

Preferred qualifications:

• Experience coordinating with EDA vendors for system maintenance, firmware updates, hardware repair, and SLA management.
• Proficiency in scripting (Python/Bash) for lab automation, system health monitoring, and performance data analysis at scale.
• Excellent problem solving skills in troubleshooting system-level hardware failures and optimizing uptime/Mean Time To Repair (MTTR) metrics.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be instrumental in sustaining operational stability and enabling the rapid expansion of the emulation infrastructure for CI2 across two emulation labs. You will manage rapidly growing install base of over 50 racks of specialized hardware from vendors like Cadence and Synopsys, along with multiple corporate and production hosts, all requiring specialized care and feeding.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead the physical and logical planning for new emulator installations and system reconfigurations.
• Collaborate with Electronic design automation (EDA) vendors to install, integrate, and maintain emulation systems.
  
• Align with engineering stakeholders to forecast emulation capacity requirements, ensuring fleet availability supports long-term product development roadmaps and schedules.
• Oversee the full system life-cycle, including the end-of-life (EOL) of older systems and the onboarding of new generations.
• Configure and manage the life-cycle of runtime corporate and production hosts, Lab network connectivity and specialized hardware (e.g., speedbridges, IO boards).