Wafer Fab Process Engineer will work in the class 100 semiconductor facility and will perform multiple operations including: cleaning and coating wafers; aligning wafers using mask aligners, metal/dielectric deposition and etching, baking and annealing, inspections, performing tool calibrations, carry out DOE runs analyze and report data.Working hours will be 10:00am – 7:00pm with flexibility to cover portion of the second shift as needed Experience:Candidate must have 2+ years experience with contact/stepper lithography, e-beam evaporation/ Sputtering, lift-off process, RTP, Furnace anneal, ALD, PECVD of SiO2 and Si3N4 and RIE/ICP processes of dielectrics and semiconductors materials. Education:BS in Science, Engineering or equivalent.
Power Integrations is committed to building teams that drive innovation and therefore review a range of factors when determining compensation. The annual base pay range for this position is $65,000 0 - $90,000. Our salary ranges are determined by role, level, qualifications and work location. The range displayed on the job posting reflects the minimum and maximum target for new hire salaries for this position in California. Within the range, individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Power Integrations also offers to our eligible employees a comprehensive total rewards package that includes equity, medical benefits, ESPP, 401K, tuition reimbursement and time off programs. https://www.power.com/company/our-sustainability-priorities/people-our-engine-innovation.
