Senior Emulation Engineer – VELOCE / ZEBU / Palladium (Automotive SoC)
NXP is looking for a STAFF‑level Emulation Engineer with 5–10 years of hands‑on experience in SoC emulation to work on cutting‑edge automotive MCUs/SoCs. This role focuses on leading pre‑silicon validation and software execution on industry‑leading emulation platforms for advanced, low‑power automotive designs.
Key Responsibilities
- Lead SoC‑level emulation bring‑up, execution, and debug on
Mentor/Siemens VELOCE, Synopsys ZEBU, and Cadence Palladium - Own emulation build creation, configuration, partitioning, and optimization for complex automotive SoCs
- Enable and debug pre‑silicon software flows using JTAG / SWD interfaces and LTB or any other debuggers
- Execute application‑specific automotive use cases including boot flows, peripherals, power modes, and safety scenarios on emulation builds
- Drive low‑power validation and debug, including power‑up/power‑down sequences
- Debug and validate clock and reset architectures, including clock trees, clock gating, reset sequencing, and cross‑domain interactions
- Enable and debug multi‑core ARM boot flows, including primary/secondary core bring‑up, synchronization, and hand‑off sequences
- Collaborate closely with RTL, SoC verification, firmware, system, and IP teams
- Provide technical leadership and mentoring across emulation activities and methodologies
Required Skills & Experience
- 3–6 years of experience in SoC Emulation, with strong hands‑on exposure to
Synopsys ZEBU, Mentor/Siemens VELOCE, and/or Cadence Palladium - Proven expertise in emulation build generation, bring‑up, and execution
- Strong debugging skills using JTAG / SWD and LTB debuggers
- Hands‑on experience working on ARM‑based automotive SoCs, including
Cortex‑M7, Cortex‑M4, Cortex‑M0+, and Cortex‑R52 cores - Solid understanding of clocking and reset architectures, including reset dependency modeling and clock domain interactions
- Strong knowledge of multi‑core ARM booting concepts, core enablement, reset vectors, and inter‑core coordination
- Solid understanding of low‑power SoC/MCU architectures, power states, clocks, and resets
- Ability to execute and debug realistic software and application workloads on emulation
- SoC Verification experience (UVM / simulation / regression debug) is a strong plus
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