Ventana is building the highest-performance RISC-V CPUs on the planet—designed for data center, AI, and edge workloads, with real silicon, not slideware.Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64-bit ARM server processor (X-Gene at AppliedMicro)—bringing decades of CPU innovation to a clean-slate, open-standards future. You can check us out here: Ventana Micro - YouTubeWe’re looking for senior microarchitects and logic designers to help define and deliver the heart of our next-gen cores. If you’ve owned major features in a high-performance CPU, we want to talk.CPU Micro Architect /Logic Designer Responsibilities:
Develop and refine microarchitecture, write design specifications, and deliver and maintain RTL for CPU Core and/or system-level sub-units
Work with physical design engineers to physically realize Core/subsystem RTL using deep sub-micron process technologies
Work with design verification/validation engineers to effectively test and debug Core/subsystem-level RTL in simulation, prototyping platforms, and silicon
Help model, analyze, debug, and address performance issues and opportunities
Qualifications Required:
8+ years industry experience working on RTL for high performance CPU or GPU, memory subsystem, or related system-level designs
Bachelors or Masters degree in related engineering field
Ability to work independently and across geographies
Strong domain knowledge of computer architecture
Skills Desired:
Verilog/SystemVerilog development experience
Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems
Experience with high frequency design considerations (timing, power, multiple clock domains, etc.)
Experience with typical front-end tools including: Verilog simulators, waveform viewers, and linting tools, as well as logic synthesis and place and route
Experience in compiled and/or interpreted (Python, perl) languages
Unit or feature ownership throughout the project lifecycle
Post-silicon validation
Bachelors or Masters degree in computer science or related engineering fields
EEOE Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law.COVID-19 Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/ business partners. NOTICE: External Recruiters/ Staffing Agencies: Ventana Micro instructs agencies not to engage with its employees to present candidates. Employees are not authorized to enter into any agreement regarding the placement of candidates. All unsolicited resumes received as gratuitous submissions. We reserve the right to directly contact any candidate speculatively submitted by a third party. Such contact will not constitute acceptance of any contractual arrangement between Ventana and the agency, and Ventana will not be liable for any fees should it choose to engage the candidate’s services. All external recruiters and staffing agencies are required to have a valid contract executed by Ventana’s CFO.Please Note: Fraudulent job postings/job scams are increasingly common. Our open positions can be found through the careers page on our website.
