Annapurna Labs, an Amazon team, designs and delivers high-end, custom silicon at the heart of AWS. Our chips don't just support the cloud; they define it. From Trainium, the purpose-built ML accelerator driving the next wave of AI innovation, to Graviton, the Arm-based server processor redefining price-performance for compute workloads, to Nitro, the advanced network and cloud management controller that underpins every AWS instance, Annapurna's products set the standard for the industry.
We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match — powering hundreds of thousands of businesses across 190 countries.
If you want to build silicon that leads the cloud world, this is where it happens.
As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.
Watch these videos to learn more about Annapurna Labs and the Nitro project:
AWS re:Invent 2025 – Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0
AWS re:Invent 2025 – Deep Dive into the AWS Nitro System: https://www.youtube.com/watch?v=cD1mNQ9YbeA
Key job responsibilities
* Full ownership of one or more IPs within the product:
- Micro-architecture definition
- RTL coding and debug
- Synthesis and timing closure
- Sign-off before tape-out
* Supporting the Verification and Emulation teams: Test plan development, coverage review
* Ensuring the chip meets quality and reliability standards
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design
Basic Qualifications
- 6+ years of experience in chip design
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog)
- Scripting expertise in C*, Perl, Python, or TCL
- BSc in Computer/Electrical Engineering
- Strong communication and collaboration skills
- Strong leadership skills and ability to own complex units
Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe)
- Experience with Network-on-Chip (NOC) architecture
- knowledge with coherent and non-coherent fabric design
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint)
- Knowledge of Design Automation tools and techniques
- Advanced degree in related technical field
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