Position:

Technical Lead (Level 1)

Job Description:

      The candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis

      Implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process 

      The ideal candidate should have thorough understanding of the end-to-end digital design

      Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog

Location:

IN-KA-Bangalore, India (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services