We are seeking a Design Verification (DV) Intern who is passionate about shaping their career path in the FPGA design and verification industry.• Collaborate with design team to understand design implementation and define verification requirement.• Work with senior DV engineers on functional verification tasks, including test planning, test creation, and coverage closure.• Implement functional coverage, assertion, tests and sequence libraries following UVM methodology.
Requirements:• Good understanding of verification process from test planning to coverage completion.• Strong communication and analytical skills.• Basic understanding of HDL (Verilog, SystemVerilog).• Proficient programming skills (e.g.: C/C++, Perl, TCL or Python).• Familiarity with FPGA is a plus.
Education and General:• Currently pursuing Electronic or Electrical Enginnering or related engineering field.• Independent and self-motivated, capable of executing under dynamic environment and uncertainties