Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 4 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
- Experience capturing design specifications in a temporal assertion language (e.g., SystemVerilog Assertions (SVA) or Property Specification Language (PSL).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science, or a related technical field.
- Experience with scripting languages (e.g., Python).
- Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
- Knowledge of formal verification algorithms.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Design the formal verification strategy and design properties and constraints for digital design blocks.
- Deploy formal property verification tools alongside formal verification closure techniques to verify properties.
- Resolve difficulty to verify properties, and contribute improvements to methodologies to enhance formal verification results.
- Implement reusable formal verification components.
