EntryFull TimeEN
Summary
Entry-level role focused on developing, executing, and automating device modeling tests within Altera Quartus Prime flows. You will validate FPGA device models, timing models, and related collateral used by synthesis, place-and-route, and timing analysis. The role blends FPGA design fundamentals, EDA flow execution, software development, and test automation to ensure model quality, correctness, and regression stability across device families.
Key Responsibilities
Test Planning and Execution
Develop test plans for device and timing model validation across Quartus Prime components (Compilation, Fitter, TimeQuest, Assembler).
Execute targeted and regression tests for multiple FPGA device families, configurations, and corner conditions.
Validate constraints (SDC) interpretation, timing arcs, and model parameterization consistency.
Flow and Infrastructure
Build and run end-to-end Quartus projects to exercise synthesis, fitting, and timing signoff on representative designs.
Maintain golden reference results; compare and triage deltas in QoR, timing, resource utilization, and warnings/errors.
Package and maintain reproducible test kits and reference designs.
Automation, Tooling, and Modeling
Create and maintain automation and modeling tools using C++, Tcl, Python, and bash for test generation, execution, log mining, and results reporting.
Develop and maintain C++ device model libraries representing FPGA architecture blocks such as DSP and memory used by synthesis and timing flows.
Integrate tests and model validation into CI pipelines (e.g., Jenkins/GitLab CI), including pass/fail gates and artifact tracking.
Develop utilities to parameterize devices, architectural variants, corners, and random seeds for coverage expansion.
Debug and Quality
Analyze failures across synthesis, fitter, timing, and device models; isolate root causes across RTL, constraints, tool behavior, and C++ model implementations.
Collaborate with modeling, device, and software teams to validate fixes and prevent regressions.
Track quality metrics (pass rate, coverage, defect density) and drive continuous improvement.
Documentation and Process
Author and update test plans, runbooks, and user guides for test environments.
Contribute to checklists and acceptance criteria for device and model signoff.
Minimum Qualifications
BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field (within 1 year of graduation).
Foundation in digital design principles: combinational/sequential logic, clocking, resets, pipelining.
Exposure to FPGA or ASIC flows: RTL (Verilog/SystemVerilog or VHDL), synthesis, static timing analysis, and constraints (SDC).
Proficiency in at least one scripting language (Tcl or Python) and a working foundation in C++ for developing or debugging hardware or device models.
Familiarity with Linux development environments and build workflows.
Strong problem-solving skills with the ability to interpret tool logs and timing reports.
Effective written communication for documentation and clear defect reporting.
Preferred Qualifications
Experience developing or maintaining C++ libraries for hardware, architectural, or device modeling (e.g., DSP, memory, or timing models).
Experience with Altera Quartus Prime (Lite/Standard/Pro), including TimeQuest and basic fitter concepts.
Hands-on experience with version control (Git) and CI systems (Jenkins/GitLab CI).
Familiarity with device concepts such as speed grades, PVT corners, IO standards, and clocking networks.
Basic understanding of timing signoff concepts (clocks, generated clocks, I/O delays, false/multicycle paths).
Coursework or projects involving FPGA boards, EDA tools, or regression test environments.
