SeniorFull TimeEN
Key Responsibilities
DFT Architecture & Strategy Leadership
Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms
Drive DFT requirements at architecture and RTL definition stages, influencing design trade-offs early
Own DFT methodology evolution, including scalability, reuse, and long-term roadmap alignment
Lead design reviews and collaborate with stakeholders to drive closure
Advanced DFT Implementation & Sign-Off
Provide hands-on leadership for complex DFT implementations, including but not limited to Scan Architecture, Scan Insertion, ATPG pattern generation and coverage analysis, Cell-Aware, Power Aware, Memory BIST and Repair, Streaming Scan Network (SSN), ICL extraction & PDL retargeting, etc.
Strong knowledge on industrial test standards IEEE 1149.1 (JTAG) and/or IEEE 1687 (IJTAG)
Drive DFT sign-off quality using tools such as SpyGlassDFT or equivalent
Resolve complex testability, clocking, and reset challenges across large designs
Timing, Physical Design & Power
Define and review DFT-related timing constraints across multiple clock domains
Partner with front end & physical design teams to achieve timing closure for scan and test logic
Address congestion, clock integrity, and DFT test-mode issues
Lead DFT improvement strategies in timing & power optimization strategies and low-power DFT solutions
Post-Silicon, Yield & Manufacturing Excellence
Lead DFT design to collaborate with post-silicon team on silicon power on, debug, failure analysis, yield improvement initiatives using silicon learning and test data
Support the initiatives of test cost optimization, coverage improvement, and DFT test hole reduction from system to tester
Collaborate deeply with Test Engineering and ATE teams, influencing tester strategies, test hardware design and flows
Functional Safety & Quality
Familiar with industrial Functional Safety standards to provide leadership in Functional Safety design related DFT strategies
Define & drive the DFT implementation to support diagnostic coverage, safety mechanisms, and compliance goals
Review and guide safety-related test concepts and documentation
Technical Leadership & Mentorship
Mentor and guide Senior and Junior DFT engineers
Set technical standards, review implementations, and raise overall DFT quality
Act as a go-to expert for complex DFT and testability issues across teams
Influence stakeholders across design, validation, manufacturing, and program management
Required Qualifications
Bachelor’s or Master’s degree in Electrical / Electronic Engineering or related field
10+ years of industry experience in DFT design, with significant hands-on ownership
Strong experience in DFT methodology, architecture & design in custom design blocks & PNR flows
Proven ability to drive collaboration across architecture, RTL, PD, test, and manufacturing teams
Strong Verilog and/or SystemVerilog proficiency
Excellent technical communication and decision-making skills
Good debugging, problem-solving, and communication skills
Proven track record in driving AI or LLM to simplify or enhance DFT implementations in FPGA or SOC design
Preferred / Differentiating Qualifications
Demonstrated leadership in DFT architecture definition for large or complex FPGA & SOC designs
Strong experience with post-silicon debug, yield ramp, and production issues
Hands-on exposure to industrial ATE platforms and tester limitations
Hands-on experience in DFT design verification is a plus
Experience driving DFT methodologies, flow development, or infrastructure improvements
Expertise in low-power DFT and test power management
Scripting and automation skills (Python, Tcl, Perl)
Experience influencing multi-site or global teams
